The present invention relates to a device for emulating designs for integrated circuits.
A common method of verifying designs for integrated circuits, or chip designs, is imaging them using programmable hardware. Such programmable hardware is frequently constructed from programmable logic circuits, or FPGA circuits (FPGA: field programmable gate array). The procedure of verification on such hardware is referred to as “emulation” or “rapid prototyping”.
Since, due to the size and complexity of a design, it is not always possible to image the entire design in only one single programmable logic circuit, programmable hardware is used which is made of multiple programmable logic circuits. A problem arising in this case is the suitable interconnection of the logic circuits with one another. If only two logic circuits are connected to one another, this connection may be constructed easily as a one-to-one interconnection. However, if three logic circuits are to be connected to one another, they may be connected either in a star structure, in a triangular structure, or in a mixed form. Multiple line intersections arise even in this case, which must be housed optimally on the circuit board which accommodates the logic circuits. The more programmable logic circuits which must be used in order to verify a chip design, the more complicated the structures become. If these structures are now imaged on a circuit board produced especially for the application, essentially two disadvantages result:                the structure must already be fixed during circuit design and layout of the circuit board. Since, however, the chip design to be verified is usually still in development at this point in time, it is extremely difficult to produce a layout of the circuit board beforehand. Furthermore, problems arise if, due to changes in the development, the necessary structure changes, so that the circuit board must then be modified;        a circuit board manufactured for a special application may typically not be used for future applications, since there are then still other requirements for the connection structure.        
A method of using an electronic reconfigurable gate field logic and a device produced by it, in which the logic circuits are connected to one another via a crossbar circuit arrangement (arrangement of crossbar chips), is known from European Patent 0 651 343.
However, this achievement of the object using crossbar circuits is not very advantageous, since crossbar circuits are special circuits which have a limited field of use and whose availability on the market is not always guaranteed. In addition, the corresponding housing of the crossbar circuit chips and its construction become more complex the greater the number of lines to be connected is. Correspondingly, the circuit board design for chips of this type is also extremely complex. Due to the high complexity of these crossbar circuit chips, in which every signal may be connected to every signal, only relatively long transfer times of the signals are achieved. In the present application, this has a direct influence on the verification speed and the verification time, in that the verification speed sinks and the verification time rises. However, the goal in the emulation of designs for integrated circuits is to verify the chip design using the highest possible speed and therefore to minimize the verification time.